@prefix rdf: . @prefix rdfs: . @prefix owl: . @prefix skos: . @prefix xl: . @prefix rdag1: . @prefix rda: . @prefix rdaa: . @prefix frbrent: . @prefix foaf: . @prefix ndl: . @prefix dct: . foaf:primaryTopic ; rdf:type ; dct:modified "2023-12-12T11:32:31"; dct:created "2023-12-12"; xl:prefLabel [xl:literalForm "寺澤, 真一";ndl:transcription "テラサワ, シンイチ"@ja-Kana,"Terasawa, Shin'ichi"@ja-Latn]; rdfs:label "寺澤, 真一"; dct:source "SystemVerilogによるFPGA/ディジタル回路設計入門, 2023.11"; skos:exactMatch ; skos:inScheme . rdf:type ; foaf:name "寺澤真一"; rda:professionOrOccupation "大学教員".