{
    "@context": "https://id.ndl.go.jp/auth/context.json",
    "uri": "http://id.ndl.go.jp/auth/ndlsh/001328304",
    "type": {
        "uri": "http://www.w3.org/2004/02/skos/core#Concept"
    },
    "modified": "2019-10-02T08:41:17",
    "created": "2019-09-02",
    "prefLabel": {
        "literalForm": "FPGA"
    },
    "label": "FPGA",
    "altLabel": [
        {
            "literalForm": "Field programmable gate arrays"
        }
    ],
    "source": [
        "実習Verilog-HDL論理回路設計, 2001.11",
        "情報・知識imidas (20190902)"
    ],
    "inScheme": {
        "uri": "http://id.ndl.go.jp/auth#topicalTerms"
    },
    "sameAs": {
        "uri": "http://id.ndl.go.jp/auth/ndlsh/FPGA"
    },
    "relatedMatch": [
        {
            "uri": "http://id.ndl.go.jp/class/ndlc/ND386"
        },
        {
            "uri": "http://id.ndl.go.jp/class/ndc10/549.7"
        }
    ],
    "broader": [
        {
            "uri": "http://id.ndl.go.jp/auth/ndlsh/01088511",
            "label": "大規模集積回路"
        }
    ],
    "closeMatch": [
        {
            "uri": "http://id.loc.gov/authorities/subjects/sh93009062"
        }
    ]
}

