3次元実装IC内ダイ間論理信号線の断線に対する電気テスト用回路 (次世代電子機器を支える三次元積層技術と先端実装の設計・評価技術論文特集)

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3次元実装IC内ダイ間論理信号線の断線に対する電気テスト用回路

(次世代電子機器を支える三次元積層技術と先端実装の設計・評価技術論文特集)

Call No. (NDL)
Z16-607
Bibliographic ID of National Diet Library
024977268
Material type
記事
Author
橋爪 正樹ほか
Publisher
東京 : 電子情報通信学会エレクトロニクスソサイエティ
Publication date
2013-11
Material Format
Paper
Journal name
電子情報通信学会論文誌. C, エレクトロニクス = The IEICE transactions on electronics. C / 電子情報通信学会 編 96(11)=551:2013.11
Publication Page
p.361-370
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Paper

Material Type
記事
Author/Editor
橋爪 正樹
小西 朝陽
四柳 浩之
Alternative Title
Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs
Periodical title
電子情報通信学会論文誌. C, エレクトロニクス = The IEICE transactions on electronics. C / 電子情報通信学会 編
No. or year of volume/issue
96(11)=551:2013.11
Volume
96
Issue
11