FPGAの動的部分再構成を利用した進化型高速パターン認識ハードウェア

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FPGAの動的部分再構成を利用した進化型高速パターン認識ハードウェア

Call No. (NDL)
Z16-779
Bibliographic ID of National Diet Library
10892893
Material type
記事
Author
川合 浩之ほか
Publisher
東京 : 電子情報通信学会情報・システムソサイエティ
Publication date
2010-11
Material Format
Paper
Journal name
電子情報通信学会論文誌. D, 情報・システム = The IEICE transactions on information and systems / 電子情報通信学会 編 93(11) (通号 467) 2010.11
Publication Page
p.2354~2367
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Paper Digital

Material Type
記事
Author/Editor
川合 浩之
山口 佳樹
安永 守利
Alternative Title
Development of high-speed evolvable pattern recognition hardware using dynamic and partial reconfiguration
Periodical title
電子情報通信学会論文誌. D, 情報・システム = The IEICE transactions on information and systems / 電子情報通信学会 編
No. or year of volume/issue
93(11) (通号 467) 2010.11
Volume
93
Issue
11
Sequential issue number
467