Help
Help
雑誌電子情報通信学会技術研究報告 : 信学技報
Volume number100(31)-100(42) 20000500-20000500
ArticleAn accurat...

An accurate RLC interconnection delay calculation for generating RC delay equivalent circuit enclosing inductance effects (特集 VLSI一般)

Icons representing 記事

An accurate RLC interconnection delay calculation for generating RC delay equivalent circuit enclosing inductance effects

(特集 VLSI一般)

Call No. (NDL)
Z16-940
Bibliographic ID of National Diet Library
5408266
Material type
記事
Author
Patrick Lenoirほか
Publisher
東京 : 電子情報通信学会
Publication date
2000-05-11
Material Format
Paper
Journal name
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 100 (通号 41) 2000.05.11
Publication Page
p.19～25
View All

Holdings of Libraries in Japan

This page shows libraries in Japan other than the National Diet Library that hold the material.

List of Cooperating Institutions and Databases

Please contact your local library for information on how to use materials or whether it is possible to request materials from the holding libraries.

other

  • CiNii Research

    Search Service
    You can check the holdings of institutions and databases with which CiNii Research is linked at the site of CiNii Research.
    Check the holdings of this book

Bibliographic Record

You can check the details of this material, its authority (keywords that refer to materials on the same subject, author's name, etc.), etc.

Paper

Material Type
記事
Title
An accurate RLC interconnection delay calculation for generating RC delay equivalent circuit enclosing inductance effects
Author/Editor
Patrick Lenoir
中村 和之
Series Title
特集 VLSI一般
Author Heading
Patrick Lenoir
中村 和之
Alternative Title
LSI上の配線におけるインダクタンス効果を組み込んだRC等価遅延モデリング
Periodical title
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
No. or year of volume/issue
100 (通号 41) 2000.05.11
Volume
100
Sequential issue number
41