ランタイムパワーゲー...

ランタイムパワーゲーティングを適用したMIPS R3000プロセッサの実装設計と評価 (システムLSI設計技術)

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ランタイムパワーゲーティングを適用したMIPS R3000プロセッサの実装設計と評価

(システムLSI設計技術)

Call No. (NDL)
Z14-1121
Bibliographic ID of National Diet Library
9373468
Material type
記事
Author
白井 利明ほか
Publisher
東京 : 情報処理学会
Publication date
2008-01
Material Format
Paper
Journal name
情報処理学会研究報告 = IPSJ SIG technical reports 2008(2) 2008.1.16・17
Publication Page
p.43~48
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Paper

Material Type
記事
Author/Editor
白井 利明
香嶋 俊裕
武田 清大 他
Alternative Title
Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating
Periodical title
情報処理学会研究報告 = IPSJ SIG technical reports
No. or year of volume/issue
2008(2) 2008.1.16・17
Volume
2008
Issue
2